1) Field of the Invention
This invention relates generally to the structure and fabrication of semiconductor devices and more particularly to the fabrication of a dielectric materials for memory devices.
2) Description of the Prior Art
A key issue for floating-gate nonvolatile semiconductor memories (NVMs) is the scaling of the tunneling oxide because the stress-induced leakage current (SILC) limits the tunnel oxide to ˜8 nm. This scaling issue is a formidable challenge especially for the emerging system-on-chip (SOC) integrated circuits designs in which programming voltage must be scaled for the NVMs to be compatible with the low voltage logic circuits. Therefore, silicon-oxide-nitride-oxide-silicon (SONOS) charge-trapping based NVM is replacing floating-gate NVM due to its advantages of lower programming voltage, smaller cell size and better endurance over the floating-gate devices. However, retention and erase speed remain as the major challenges for conventional SONOS devices as device and voltage further scale in the future.
The relevant technical developments in the literature can be are described below.
U.S. Pat. No. 6,803,275—Park, et al.—Oct. 12, 2004—NO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices.
U.S. Pat. No. 6,680,509—Wu, et al.—Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory.
U.S. Pat. No. 6,790,755—Jeon—Preparation of stack high-K gate dielectrics with nitrided layer.
Bunmi Adetutu, Jiankang Bu, Hsing Tseng, “A Novel Floating Trap NVSM”.
US 20030194853 A1—Jeon, Joong—Preparation of stack high-K gate dielectrics with nitrided layer.
U.S. Pat. No. 6,764,898B1—En et al.—shows a SONOS device with High k layers.
US 20030219947—Shin, Yoo-Cheol—Memory device and fabrication method thereof.
U.S. Pat. No. 6,740,605B1—Shiraiwa et al. shows a SONOS like device.